1. Field of the Invention
The disclosed technology relates to fault mode circuits and more particularly, although not exclusively, to full screening of through-silicon-via connections on three-dimensional integrated circuits.
2. Description of the Related Technology
The importance of testing integrated circuits (ICs) is well known and several methods have been used for carrying out such testing. US-A-2009/0224784 describes a method in which a frequency-division multiplexing scheme of test signals is used for reducing the number of input/output contact pads that need to be connected to the semiconductor wafer on which the IC is formed.
U.S. Pat. No. 7,863,106 describes a test fixture for testing wafers in which a test probe assembly provides connectivity to filled-through vias (FTVs) and a conductive glass handler is biased with an appropriate voltage for test. The test probe assembly measures the voltage drop from a top surface bond pad to a FTV to provide an indication of the integrity of the FTV. The test fixture also determines leakage resistance using an opens shorts test.
Built-in-self test (BIST) logic may be included in a three-dimensional (3D) stacked processor chip as described in US-A-2010/0185410. The BIST can test the entire assembled stacked processor chip and/or specific layers in the stack and/or components located on a specific layer. An integrated distributed test interface is built into each later so that all the layers can be tested at the same time.
It is known to check the integrity of through-silicon-via (TSV) connections in three-dimensional (3D) integrated circuits (ICs) and long tracks in mixed-signal ICs. One such apparatus and method is described in US-A-2010/0332177. A test access control apparatus and method for stacked chip devices that can perform system on chip (SOC) test and through-silicon-via (TSV) verification are disclosed. The apparatus includes test access mechanism (TAM) buses and an extended IEEE 1149.1 test access port (TAP) controller connected to the TAM buses. The TAM buses support controls of a memory built-in-self-test (BIST) circuit for memory known-good-die (KGD) tests that are carried out before the chip devices are stacked, and TSV chains for conducting TSV tests that verify any defect appearing in vertical interconnection in the stacked chip devices.
US-A-2010/0153043 also discloses monitoring apparatus for TSVs in a 3D IC. The TSVs are connected in a circuit with a plurality of inverters. A control signal is applied to the circuit to cause it to oscillate. An output signal with an oscillatory wave is generated and the frequency thereof is compared to an output signal obtained from an ideal-manufactured 3D IC having the same configuration to determine if the 3D IC being tested meets pre-defined parameters.
In US-A-2010/0013512, a method of testing TSVs is described. TSV stacks are selected to which a reference voltage source, a current source and a voltage measuring device is connected. Measurement of a voltage drop provides a relative estimation of the resistance of the TSV stack. Comparisons of the estimated resistance for each TSV stack enables the best TSV stacks to be selected for use.
Existing tests for testing TSV connections and long tracks have implementation issues. For example, there may be difficulties with probing dense TSVs individually during wafer-sort and final test processes. It is important to sort good dies from bad dies before moving onto the stacking and/or assembly stages which are relatively expensive processes. The problems associated with sorting of dies include: the inability to probe the integrity of floating TSVs on both thinned and un-thinned wafers due to missing connections; the limitation imposed the electrical tests that need to be carried out at by the requirement to handle very fragile thinned wafers during wafer-sort tests; and the limitation to static logic tests for continuity checks of the connections between tiers as it is not possible the test the quality of the contact.
In addition, it is important to detect misalignment of dies and/or wafers during the stacking process. As this forms the last process before the assembly of the stacked tiers in the final package, detecting a fault at this stage saves the expensive packaging costs. Moreover, it is necessary to detect faults that arise from long wiring between digital and analogue elements of the wafer. Most of the long tracks are prone to bridging errors which can be hard to detect via bridging tests, especially for the interfaces between analogue and digital modes. In such tests, the same track needs to be repeated for the return track to ensure that the signal has been received at its destination correctly. This adds a lot of cost as well as signal integrity issues in these mixed-mode systems.
Existing test structures have severe limitations, for example, the requirement for large silicon area to implement test circuits when used over a large number of TSVs; the need for special analogue process options; limitation to test TSVs that carry digital signals but also analogue signals; the inability to generate a meaningful test output signal that represents the integrity of TSVs; the limitation to characterization exercises on dedicated test circuits (the difficulty of integration into standard equipment or products); the imposition of large loading that limits the performance of the tier-to-tier communication; the lack of calibration of the measurements for each TSV for setting reliable limits for production tests, and the requirement for long test times over a large number of TSVs.